Toshiba Details 90nm For SOC

Toshiba claims a 100% increase in gate integration, a 20% increase in gate speed percent and a 50% reduction in power consumption, compared to the previous generation 0.13micron process technology (TC280).

Toshiba is now accepting designs with several system on chip (SOC) designs in development. The first customer samples have already been shipped.

TC300 features two types of embedded DRAM optimised for speed or density.
A range of package types for high-performance SOCs are available, including 200-2,304 pin flip chip ball grid array (FCBGA), 109-256 PFBGA chip scale package and a 256-868 pin PBGA package with a multi-layer structure.

TC300 is due to begin ramping for mass production in Q2 2003 with high-volume production expected in Q3 2003.

The 90nm CMOS4 silicon technology was jointly developed with Sony. The two companies are also working on 65nm CMOS process technology for embedded DRAM. Toshiba also has an alliance with Fujitsu on SOC collaboration. In July, Toshiba joined with ten other Japanese companies to form the Advanced SOC Platform (ASPLA) organisation to establish a standardised design and process base for 90nm technology.